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high voltage , latch - up proof, 4 - /8 - channel multiplexers data sheet adg5208/adg5209 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trad emarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2011 C 2012 analog devices, inc. all rights reserved. features latch - up proof 5.5 pf off source capacitance 52 pf off drain capacitance 0 .4 pc c harge injection low on resistance: 1 6 0 ? typ ical 9 v to 2 2 v dual - supply operation 9 v to 40 v single - supply operation 48 v supply maximum ratings fully specified at 15 v, 20 v, +12 v , and +36 v v ss to v dd analog signal range human b ody m odel ( hbm ) esd rating 4 kv i/o port to supp lies 1 kv i/o p ort to i/o p ort 4 kv a ll other pins applications automatic test equipment data acquisition instrumentation avionics aud io and video switching communication systems functional block dia grams adg5208 s1 s8 d 1-of-8 decoder a0 a1 a2 en adg5209 s1a s4a da s1b s4b db 1-of-4 decoder a0 a1 en 09917-001 figure 1. general description the adg5208 / adg5209 are mo nolit hic cmos analog multi - p lexers comprising eight single channels and four differential channels, respectively. the adg5208 switches one of eight inputs to a common output, as determined by the 3 - bit binary addre ss lines, a0, a1, and a2. the adg5209 switches one of four differential inputs to a common differential output, as determined by the 2 - bit binary address lines, a0 and a1. an en input on both devices enable s or disable s the device. when en is disabled, all channels switch off. the ultralow capacitance and charge injection of these switches make them ideal solutions for data acquisition and sample - and - hold appli - cations, where low glitch and fast settling are r equired. fast switching speed coupled with high signal bandwidth make the se devices suitable for video signal switching. each switch conducts equally well in both directions when on, and each switch has an input signal range that extends to the power supp lies. in the off condition, signal levels up to the supplies are blocked. the adg5208 / adg5209 do not have v l pins; instead , the logic power supply is generated i nternally by an on - chip voltage generator. product highlights 1. trenc h isolation guards against latch - u p. a dielectric trench separates the p and n channel transistors t o prevent latch - up even under severe overvoltage conditions . 2. 0.4 pc charge injec tion. 3. du al - supply ope ration. for applications where the analog signal is bipolar, the adg5208 / adg5209 can be operated from dual supplies of up to 2 2 v. 4. single - supply op era tion. for applications where the analog sign al is unipolar, the adg5208 / adg5209 can be operated from a single rail power supply of up to 40 v. 5. 3 v logic - comp atible digital inpu ts . v i n h = 2.0 v, v i n l = 0.8 v. 6. no v l logic power supply require d.
adg5208/adg5209 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagrams ............................................................. 1 general description ......................................................................... 1 product highlig hts ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 15 v dual supply ....................................................................... 3 20 v dual supply ....................................................................... 4 12 v single supply ........................................................................ 5 36 v single supply ........................................................................ 6 continuous current per channel, sx or dx ............................. 8 absolute maximum ratings ............................................................9 esd caution ...................................................................................9 pin configurations and function descriptions ......................... 10 typical performance characteristics ........................................... 12 test circuits ..................................................................................... 16 terminology .................................................................................... 19 trench isolation .............................................................................. 20 applications information .............................................................. 21 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 3/12 rev. 0 to rev. a added 16 - lead lfcsp ....................................................... universal changes to ordering guide ........................................................... 22 7 / 11 revision 0: initial version
data sheet adg5208/adg5209 rev. a | page 3 of 24 specifications 15 v dual supply v dd = + 15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 160 ? typ v s = 10 v, i s = ?1 ma; see figure 28 200 250 280 ? max v dd = +13.5 v, v ss = ?13.5 v on - resistance match between channels, ? r on 3.5 ? typ v s = 10 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 40 ? typ v s = 10 v, i s = ?1 ma 50 65 70 ? max le akage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage, i s (off ) 0.005 na typ v s = 10 v, v d = ? 1 0 v; see figure 30 0.1 0.2 0.4 na max drain off leakage, i d (off ) 0.005 na typ v s = 10 v, v d = ? 10 v; see figure 30 0.1 0.4 1.4 na max channel on leakage, i d (on), i s (on) 0.01 na typ v s = v d = 10 v; see figure 27 0.2 0.5 1.4 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 170 ns typ r l = 300 ?, c l = 35 pf 205 245 275 ns max v s = 10 v; see figure 33 t on (en) 145 ns typ r l = 300 ?, c l = 35 pf 185 220 245 ns max v s = 10 v; see figure 35 t off (en) 120 ns typ r l = 300 ?, c l = 35 pf 145 165 180 ns max v s = 10 v; see figure 35 break - before - make time delay, t d 65 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v; see figure 34 charge injection, q inj 0 .4 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 36 off is olation ? 9 0 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 channel - to - channel crosstalk ? 9 0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 29 ?3 db ban dwidth r l = 50 ?, c l = 5 pf; see figure 32 adg5208 54 mhz typ adg5209 133 mhz typ insertion loss ? 6.4 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 32 c s (off ) 5.5 pf typ v s = 0 v, f = 1 mhz c d (off ) adg5208 52 pf typ v s = 0 v, f = 1 mhz adg5209 26 pf typ v s = 0 v, f = 1 mhz
adg5208/adg5209 data sheet rev. a | page 4 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments c d (on), c s (on) adg5208 58 pf typ v s = 0 v, f = 1 mhz adg5209 31 pf t yp v s = 0 v, f = 1 mhz power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 45 a typ digital inputs = 0 v or v dd 55 70 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 20 v dual supply v dd = + 20 v 10%, v ss = ?20 v 10%, gnd = 0 v, unless otherwise noted. table 2 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range v dd to v ss v on resistance, r on 140 ? typ v s = 15 v, i s = ?1 ma; see figure 28 160 200 230 ? max v dd = +18 v, v ss = ?18 v on - resistance match between channels, ? r on 3 .5 ? typ v s = 15 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 34 ? typ v s = 15 v, i s = ?1 ma 45 55 60 ? max leakage currents v dd = +22 v, v ss = ?22 v source off leakage, i s (off ) 0.005 na typ v s = 15 v, v d = ? 15 v; see figure 30 0.1 0.2 0.4 na max drai n off leakage, i d (off ) 0.005 na typ v s = 15 v, v d = ? 15 v; see figure 30 0.1 0.4 1.4 na max channel on leakage, i d (on), i s (on) 0.01 na typ v s = v d = 15 v; see figure 27 0.2 0.5 1.4 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digita l input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 160 ns typ r l = 300 ?, c l = 35 pf 195 225 255 ns max v s = 10 v; see figure 33 t on (en) 145 ns typ r l = 300 ?, c l = 35 pf 170 200 225 ns max v s = 10 v; see figure 35 t off (en) 120 ns typ r l = 300 ?, c l = 35 pf 140 155 170 ns max v s = 10 v; see figure 35 break - before - make time delay, t d 55 ns typ r l = 300 ?, c l = 35 pf 30 ns min v s1 = v s2 = 10 v; see figure 34 charge injection, q inj 0 .3 pc typ v s = 0 v, r s = 0 ?, c l = 1 nf; see figure 36 off isolation ? 9 0 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 channel - to - channel crosstalk ? 9 0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 29
data sheet adg5208/adg5209 rev. a | page 5 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 32 adg5208 60 mhz typ adg5209 130 mhz typ insertion loss ? 5.6 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 32 c s (off ) 5.5 pf typ v s = 0 v, f = 1 mhz c d (off ) adg5208 51 pf typ v s = 0 v, f = 1 mhz adg5209 26 pf typ v s = 0 v, f = 1 mhz c d (on), c s (on) adg5208 57 pf typ v s = 0 v, f = 1 mhz adg5209 31 pf typ v s = 0 v, f = 1 mhz power requirements v dd = +22 v, v ss = ?22 v i dd 50 a typ digital inputs = 0 v or v dd 70 110 a max i ss 0.001 a typ digital inputs = 0 v or v dd 1 a max v dd /v ss 9/22 v min/v max gnd = 0 v 1 guaranteed by design; not subject to production test. 12 v single supply v dd = 12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwis e noted. table 3 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 350 ? typ v s = 0 v to 10 v, i s = ?1 ma; see figure 28 500 610 700 ? max v dd = 10.8 v, v ss = 0 v on - resistance match between channels, ? r on 5 ? typ v s = 0 v to 10 v, i s = ?1 ma 20 22 24 ? max on - resistance flatness, r flat (on) 160 ? typ v s = 0 v to 10 v, i s = ?1 ma 280 335 370 ? max leakage currents v dd = 13.2 v, v ss = 0 v source off leakage, i s (off ) 0.005 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 30 0.1 0.2 0.4 na max drain off leakag e, i d (off ) 0.005 na typ v s = 1 v/10 v, v d = 10 v/1 v; see figure 30 0.1 0.4 1.4 na max channel on leakage, i d (on), i s (on) 0.01 na typ v s = v d = 1 v/10 v; see figure 27 0.2 0.5 1.4 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ
adg5208/adg5209 data sheet rev. a | page 6 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments dynamic characteristics 1 transition time, t transition 210 ns typ r l = 300 ?, c l = 35 pf 270 330 380 ns max v s = 8 v; see figure 33 t on (en) 215 ns typ r l = 300 ? , c l = 35 pf 275 34 5 400 ns max v s = 8 v; see figure 35 t off (en) 115 ns typ r l = 300 ? , c l = 35 pf 140 160 175 ns max v s = 8 v; see figure 35 break - before - make time delay, t d 135 ns typ r l = 300 ? , c l = 35 pf 70 ns min v s1 = v s2 = 8 v; see figure 34 charge injection, q inj 0 .3 pc typ v s = 6 v, r s = 0 ? , c l = 1 nf; see figure 36 off isol ation ? 9 0 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 channel - to - channel crosstalk ? 9 0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 29 ?3 db bandwi dth r l = 50 ?, c l = 5 pf; see figure 32 adg5208 60 mhz typ adg5209 120 mhz typ insertion loss ? 8.8 db ty p r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 32 c s (off ) 6 pf typ v s = 6 v, f = 1 mhz c d (off ) adg5208 56 pf typ v s = 6 v, f = 1 mhz adg5209 28 pf typ v s = 6 v, f = 1 mhz c d (on), c s (on) adg5208 63 pf typ v s = 6 v, f = 1 mhz adg5209 35 pf typ v s = 6 v, f = 1 mhz power requirements v dd = 13.2 v i dd 40 a typ digital inputs = 0 v or v dd 50 65 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test. 36 v single supply v dd = 36 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. t able 4 . parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments analog switch analog signal range 0 v to v dd v on resistance, r on 150 ? typ v s = 0 v to 30 v, i s = ?1 ma; see figure 28 170 215 245 ? max v dd = 32.4 v, v ss = 0 v on - resistance match between channels, ? r on 3.5 ? typ v s = 0 v to 30 v, i s = ?1 ma 8 9 10 ? max on - resistance flatness, r flat (on) 35 ? typ v s = 0 v to 30 v, i s = ?1 ma 55 65 70 ? max leakage currents v dd = 39.6 v, v ss = 0 v source off leakage, i s (off ) 0.005 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 30 0.1 0.2 0.4 na max
data sheet adg5208/adg5209 rev. a | page 7 of 24 parameter 25c ?40c to +85c ?40c to +125c unit test conditions/comments drain off leakage, i d (off ) 0.005 na typ v s = 1 v/30 v, v d = 30 v/1 v; see figure 30 0.1 0.4 1.4 na max channel on leakage, i d (on), i s (on) 0.01 na typ v s = v d = 1 v/30 v; see figure 27 0.2 0.5 1.4 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl 0.8 v max input current, i inl or i inh 0.002 a typ v in = v gnd or v dd 0.1 a max digital input capacitance, c in 3 pf typ dynamic characteristics 1 transition time, t transition 185 ns typ r l = 300 ?, c l = 35 pf 230 245 259 ns max v s = 18 v; see figure 33 t on (en) 170 ns typ r l = 300 ? , c l = 35 pf 210 230 255 ns max v s = 18 v; see figure 35 t off (en) 125 ns typ r l = 300 ? , c l = 35 pf 180 180 180 ns max v s = 18 v; see figure 35 break - before - make time delay, t d 70 ns typ r l = 300 ? , c l = 35 pf 35 ns min v s1 = v s2 = 18 v; see figure 34 charge injection, q inj 0 .4 pc typ v s = 18 v, r s = 0 ? , c l = 1 nf; see figure 36 off isolation ? 9 0 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 31 channel - to - channel crosstalk ? 9 0 db typ r l = 50 ? , c l = 5 pf, f = 1 mhz; see figure 29 ?3 db bandwidth r l = 50 ?, c l = 5 pf; see figure 32 adg5208 65 mhz typ adg5209 130 mhz typ insertion loss ? 6 db typ r l = 50 ?, c l = 5 pf, f = 1 mhz; see figure 32 c s (off ) 5.5 pf typ v s = 18 v, f = 1 mhz c d (off ) adg5208 51 pf typ v s = 18 v, f = 1 mhz adg5209 25 pf typ v s = 18 v, f = 1 mhz c d (on), c s (on) adg5208 57 pf typ v s = 18 v, f = 1 mhz adg5209 32 pf typ v s = 18 v, f = 1 mhz power requirements v dd = 39.6 v i dd 80 a typ digital inputs = 0 v or v dd 100 130 a max v dd 9/40 v min/v max gnd = 0 v, v ss = 0 v 1 guaranteed by design; not subject to production test.
adg5208/adg5209 data sheet rev. a | page 8 of 24 continuous current p er channel, s x , d, or d x table 5 . adg5208 parameter 25c 85c 125c unit continuous current, sx or d v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 40 24 14.5 ma maximum lfcsp ( ja = 30.4c/w) 69 37 18 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 42 26.5 14.5 ma maximum lfcsp ( ja = 30.4c/w) 75 40 18 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 28 19 12 ma maximum lfcsp ( ja = 30.4c/w) 40 25 14.5 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 40 26 14.5 ma maximum lfcsp ( ja = 30.4c/w) 72 39 18 ma maximum table 6 . adg5209 parameter 25c 85c 125c unit continuous current, sx or d x v dd = +15 v, v ss = ?15 v tssop ( ja = 112.6c/w) 29 19 12 ma maximum lfcsp ( ja = 30.4c/w) 51 30 16 ma maximum v dd = +20 v, v ss = ?20 v tssop ( ja = 112.6c/w) 30 20 12.5 ma maximum lfcsp ( ja = 30.4c/w) 55 32 17 ma maximum v dd = 12 v, v ss = 0 v tssop ( ja = 112.6c/w) 20 14 10 ma maximum lfcsp ( ja = 30.4c/w) 29 20 12.5 ma maximum v dd = 36 v, v ss = 0 v tssop ( ja = 112.6c/w) 30 20 12.5 ma maximum lfcsp ( ja = 30.4c/w) 54 31 17 ma maximum
data sheet adg5208/adg5209 rev. a | page 9 of 24 absolute maximum rat ings t a = 25c, unless otherwise noted. table 7 . parameter rating v dd to v ss 48 v v dd to gnd ?0.3 v to +48 v v ss to gnd +0.3 v to ?48 v analog inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first digital inputs 1 v ss ? 0.3 v to v dd + 0.3 v or 30 ma, whichever occurs first peak current, sx , d, or d x pins adg5208 126 ma (pulsed at 1 ms, 10% duty cycle maximum) adg5209 92 ma (pulsed at 1 ms, 10% duty cycle maximum) continuous current, s x , d, or d x pins 2 data + 15% temperature range operating ?40c to +125c storage ?65c to +150c junction temperature 150c thermal impedance, ja 16- lead tssop (4 - layer board) 112.6c/w 16- lead lfcsp (4 - layer board) 30.4c/w reflow soldering peak temperature, pb free 260(+0/?5)c hbm esd i/o port to supp lies 4 kv i/o port to i/o port 1 kv all other pi ns 4 kv 1 overvoltages at the a x, en, sx, d, and d x pins are clamped by internal diodes. limit current to the maximum ratings given. 2 see table 5 and table 6 . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in dicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating can be applied at any one time. esd caution
adg5208/adg5209 data sheet rev. a | page 10 of 24 pin configurations a nd function descript ions a0 1 en 2 v ss 3 s1 4 a1 16 a2 15 gnd 14 v dd 13 s2 5 s5 12 s3 6 s6 11 s4 7 s7 10 d 8 s8 9 adg5208 top view (not to scale) 09917-002 figure 2. adg5208 pin configuration (tssop) 12 11 10 1 3 4 gnd v dd s5 9 s6 v ss s2 2 s1 s3 6 d 5 s4 7 s8 8 s7 16 en 15 a0 14 a1 13 a2 top view (not to scale) adg5208 notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 09917-003 figure 3. ad g5208 pin configuration (lfcsp) table 8 . adg5208 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital inp ut. when low, the device is disabled and all switches are off. when high, the ax logic inputs determine the on switches. 3 1 v ss most negative power supply potential. in single - supply applications, this pin can be connected to ground. 4 2 s1 source term inal 1. this pin c an be an input or an output. 5 3 s2 source terminal 2. this pin can be an input or an output. 6 4 s3 source terminal 3. this pin can be an input or an output. 7 5 s4 source terminal 4. this pin can be an input or an output. 8 6 d drai n terminal. this pin can be an input or an output. 9 7 s8 source terminal 8. this pin can be an input or an output. 10 8 s7 source terminal 7. this pin can be an input or an output. 11 9 s6 source terminal 6. this pin can be an input or an output. 12 1 0 s5 source terminal 5. this pin can be an input or an output. 13 11 v dd most positive power supply potential. 14 12 gnd ground (0 v) reference. 15 13 a2 logic control input. 16 14 a1 logic control input. ep exposed pad the exposed pad is connected i nternally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 9 . adg5208 truth tabl e a2 a1 a0 en on switch x 1 x 1 x 1 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8 1 x is dont care.
data sheet adg5208/adg5209 rev. a | page 11 of 24 a0 1 en 2 v ss 3 s1a 4 a1 16 gnd 15 v dd 14 s1b 13 s2a 5 s2b 12 s3a 6 s3b 11 s4a 7 s4b 10 da 8 db 9 adg5209 top view (not to scale) 09917-004 figure 4. adg5209 pin configuration (tssop) 12 11 10 1 3 4 v dd s1b s2b 9 s3b v ss s2a 2 s1a s3a 6 da 5 s4a 7 db 8 s4b 16 en 15 a0 14 a1 13 gnd top view (not to scale) adg5209 notes 1. the exposed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . 09917-005 figure 5. adg5209 pin configuration (lfcsp) table 10. adg5209 pin function descriptions pin no. tssop lfcsp mnemonic description 1 15 a0 logic control input. 2 16 en active high digital input. when low, the device is disa bled and all switches are off. when high, ax logic inputs determine the on switches. 3 1 v ss most negative power supply potential. in single - supply applications, this pin can be connected to ground. 4 2 s1a source terminal 1a. this pin c an be an input or an output. 5 3 s2a source terminal 2a. this pin can be an input or an output. 6 4 s3a source terminal 3a. this pin can be an input or an output. 7 5 s4a source terminal 4a. this pin can be an input or an output. 8 6 da drain terminal a. this pin can be an input or an output. 9 7 db drain terminal b. this pin can be an input or an output. 10 8 s4b source terminal 4b. this pin can be an input or an output. 11 9 s3b source terminal 3b. this pin can be an input or an output. 12 10 s2b source terminal 2b. this pin can be an input or an output. 13 11 s1b source terminal 1b. this pin can be an input or an output. 14 12 v dd most positive power supply potential. 15 13 gnd ground (0 v) reference. 16 14 a1 logic control input. ep exposed pad the expos ed pad is connected internally. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the substrate, v ss . table 11. adg5209 truth table a1 a0 en on switch pair x 1 x 1 0 none 0 0 1 1 0 1 1 2 1 0 1 3 1 1 1 4 1 x is dont care.
adg5208/adg5209 data sheet rev. a | page 12 of 24 typical performance characteristics 160 0 20 40 60 80 100 120 140 ?25 ?20 ?15 ?10 ?5 0 5 10 15 20 25 on resistance (?) v s , v d (v) t a = 25c v dd = +18v v ss = ?18v v dd = +20v v ss = ?20v v dd = +22v v ss = ?22v 09917-006 figure 6. r on as a func tion of v s , v d ( 20 v dual supply ) 250 200 150 100 50 0 ?20 ?15 ?10 ?5 0 5 10 15 20 on resistance (?) v s , v d (v) t a = 25c v dd = +9v v ss = ?9v v dd = +13.2v v ss = ?13.2v v dd = +15v v ss = ?15v v dd = +16.5v v ss = ?16.5v 09917-007 figure 7. r on as a function of v s , v d ( 15 v dual supply) 500 450 400 350 300 250 200 150 100 50 0 0 14 12 10 8 6 4 2 on resistance (?) v s , v d (v) t a = 25c v dd = 9v v ss = 0v v dd = 10.8v v ss = 0v v dd = 12v v ss = 0v v dd = 13.2v v ss = 0v 09917-008 figure 8. r on as a function of v s , v d ( 12 v single supply) 160 140 120 100 80 60 40 20 0 0 40 35 30 25 20 15 10 5 on resistance (?) v s , v d (v) t a = 25c v dd = 32.4v v ss = 0v v dd = 36v v ss = 0v v dd = 39.6v v ss = 0v 09917-009 figure 9. r on a s a function of v s , v d ( 36 v single supply) 250 200 150 100 50 0 ?15 ?10 ?5 0 5 10 15 on resistance (?) v s, v d (v) v dd = +15v v ss = ?15v t a = +125c t a = +85c t a = +25c t a = ?40c 09917-010 figure 10 . r on as a function of v s , v d for different temperatures, 15 v dual supply 200 160 120 80 40 180 140 100 60 20 0 ?20 ?15 ?10 ?5 0 5 10 20 15 on resistance (?) v s, v d (v) v dd = +20v v ss = ?20v t a = +125c t a = +85c t a = +25c t a = ?40c 09917-0 1 1 figure 11 . r on as a function of v s , v d for different temperatures, 20 v dual supply
data sheet adg5208/adg5209 rev. a | page 13 of 24 500 400 300 200 100 450 350 250 150 50 0 0 2 4 6 8 10 12 on resistance (?) v s, v d (v) v dd = 12v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09917-012 figure 12 . r on as a function of v s , v d for different temperatures, 12 v single supply 250 200 100 150 50 0 0 35 30 25 20 15 10 5 on resistance (?) v s, v d (v) v dd = 36v v ss = 0v t a = +125c t a = +85c t a = +25c t a = ?40c 09917-013 figure 13 . r on as a function of v s , v d for different temperatures, 36 v single supply 50 ?250 ?200 ?150 ?100 ?50 0 0 125 100 75 50 25 leakage current (pa) temperature (c) v dd = +15v v ss = ?15v v bias = +10v/?10v i s (off) + ? i s (off) ? + i d , i s (on) + + i d (off) + ? i d (off) ? + i d , i s (on) ? ? 09917-014 fi gure 14 . leakage currents vs. temperature, 15 v dual supply 100 ?200 ?150 ?100 ?50 0 50 0 125 100 75 50 25 leakage current (pa) temperature (c) v dd = +20v v ss = ?20v v bias = +15v/?15v i s (off) + ? i s (off) ? + i d , i s (on) + + i d (off) + ? i d (off) ? + i d , i s (on) ? ? 09917-015 figure 15 . leakage currents vs. temperature, 20 v dual supply 100 ?700 ?600 ?500 ?400 ?300 ?200 ?100 0 0 125 100 75 50 25 leakage current (pa) temperature (c) v dd = 12v v ss = 0v v bias = 1v/10v i s (off) + ? i s (off) ? + i d , i s (on) + + i d (off) + ? i d (off) ? + i d , i s (on) ? ? 09917-016 figure 16 . leakage currents vs. temperature, 12 v single supply 200 ?1000 ?800 ?600 ?400 ?200 0 0 125 100 75 50 25 leakage current (pa) temperature (c) v dd = 36v v ss = 0v v bias = 1v/30v i s (off) + ? i s (off) ? + i d , i s (on) + + i d (off) + ? i d (off) ? + i d , i s (on) ? ? 09917-017 figure 17 . leakage currents vs. temperature, 36 v single supply
adg5208/adg5209 data sheet rev. a | page 14 of 24 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m off isolation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v 09917-018 figure 18 . off isolation vs. frequency, 15 v dual supply 0 ?140 ?120 ?100 ?80 ?60 ?40 ?20 10k 100k 1g 100m 10m 1m crosstalk (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v between s1 and s2 between s1 and s8 09917-019 figure 19 . crosstalk vs. freque ncy, 15 v dual supply 16 0 2 4 6 8 10 12 14 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c demux (drain to source) v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09917-020 figure 20 . charge injection vs. source voltage , drain to source 0 ?120 ?100 ?80 ?60 ?40 ?20 1k 10k 100k 10m 1m acpsrr (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v no decoupling capacitors decoupling capacitors 09917-021 figure 21 . acpsrr vs. frequency, 15 v dual supply ?6 ?12 ?11 ?10 ?9 ?8 ?7 100k 1m 10m 1g 100m attenuation (db) frequency (hz) t a = 25c v dd = +15v v ss = ?15v adg5208 adg5209 09917-023 figure 22 . bandwidth 6 ?2 ?1 0 1 2 3 4 5 ?20 ?10 0 10 20 30 40 charge injection (pc) v s (v) t a = 25c mux (source to drain) v dd = +20v v ss = ?20v v dd = +15v v ss = ?15v v dd = +36v v ss = 0v v dd = +12v v ss = 0v 09917-039 figur e 23 . charge injection vs. source voltage , source to drain
data sheet adg5208/adg5209 rev. a | page 15 of 24 350 0 50 100 150 200 250 300 ?40 ?20 0 20 40 60 80 100 120 time (ns) temperature (c) v dd = +12v v ss = 0v v dd = +15v v ss = ?15v v dd = +20v v ss = ?20v v dd = +36v v ss = 0v 09917-024 figure 24 . t transition times vs. temperature 40 35 30 25 20 15 10 5 0 ?15 ?10 15 10 5 0 ?5 capacitance (pf) v s (v) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09917-025 figure 25 . adg5209 cap acitance vs. source voltage, 15 v dual supply 80 70 60 50 40 30 20 10 0 ?15 ?10 15 10 5 0 ?5 capacitance (pf) v s (v) t a = 25c v dd = +15v v ss = ?15v source/drain on drain off source off 09917-040 figure 26 . adg5208 capacitance vs. source voltage, 15 v dual supply
adg5208/adg5209 data sheet rev. a | page 16 of 24 test circuits sx d a v d i d (on) nc nc = no connect 09917-027 figure 27 . on leak age sx d v s v1 i ds r on = v1/i ds 09917-028 figure 28 . on resistance channel-to-channel crosstalk = 20 log v out gnd s1 d s2 v out network analyzer r l 50? r l 50? v s v s v dd v ss 0.1f v dd 0.1f v ss 09917-029 figure 29 . channel - to - channel crosstalk v s v d sx d a a i s (off) i d (off) 09917-031 figure 30 . off leakage v out 50? network analyzer r l 50? sx d v s v dd v ss 0.1f v dd 0.1f v ss gnd 50? off isolation = 20 log v out v s 09917-030 figure 31 . off isolation v out 50? network analyzer r l 50? sx d insertion loss = 20 log v out with switch v out without switch v s v dd v ss 0.1f v dd 0.1f v ss gnd 09917-033 figure 32 . bandwidth
data sheet adg5208/adg5209 rev. a | page 17 of 24 3v 0v output t r < 20ns t f < 20ns address drive (v in ) t transition t transition 50% 50% 90% 90% output adg5208* a0 a1 a2 50? 300? gnd s1 s2 to s7 s8 d 35pf v in 2.0v en v dd v ss v dd v ss v s1 v s8 * similar connection for adg5209. 09917-034 figure 33 . address to output switching times, t transition output adg5208* a0 a1 a2 50? 300? gnd s1 s2 to s7 s8 d 35pf v in 2.0v en v dd v ss v dd v ss v s * similar connection for adg5209. 3v 0v output 80% 80% address drive (v in ) t d 09917-035 figure 34 . break - before - make time delay, t d output adg5208* a0 a1 a2 50? 300? gnd s1 s2 to s8 d 35pf v in en v dd v ss v dd v ss v s *similar connection for adg5209. 3v 0v output 50% 50% t off (en) t on (en) 0.9v out 0.1v out enable drive (v in ) 09917-036 figure 35 . enable delay , t on (en), t o ff (en)
adg5208/adg5209 data sheet rev. a | page 18 of 24 3v v in v out q inj = c l v out v out d s en gnd c l 1nf v out v in r s v s v dd v ss v dd v ss a0 a1 a2 adg5208* *similar connection for adg5209. 09917-037 figure 36 . charge injection
data sheet adg5208/adg5209 rev. a | page 19 of 24 terminology i dd i dd represents the positive supply current. i ss i ss represents the negative supply current. v d , v s v d and v s represent the analog voltage on terminal d and terminal s, respe ctively. r on r on is the ohmic resistance between terminal d and terminal s. ? r on ? r on represents the difference between the r on of any two channels. r flat (on) flatness that is defined as the difference between the maximum and minimum value of on resistan ce measured over the specified analog signal range is represented by r flat (on) . i s (off) i s (off) is the source leakage current with the switch off. i d (off) i d (off) is the drain leakage current with the switch off. i d (on), i s (on) i d (on) and i s ( on) represent the channel leakage currents with the switch on. v inl v inl is the maximum input voltage for logic 0. v inh v inh is the minimum input voltage for logic 1. i inl , i inh i inl and i inh represent the low and high input currents of the digital in puts. c d (off) c d (off) represents the off switch drain capacitance, which is measured with reference to ground. c s (off) c s (off) represents the off switch source capacitance, which is measured with reference to ground. c d (on), c s (on) c d (on) and c s (on) represent on switch capacitances, which are measured with reference to ground. c in c in represents digital input capacitance. t on (en) t on (en) represents the delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) t off (en) represents the delay time between the 50% and 90% points of the digital input and switch off condition. t transition t transition represents the d elay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. break - before - make time delay ( t d ) t d represents the off time measured between the 80% point of both switches when switching from one address state to another. off isolation off isolation is a measure of unwanted signal coupling through an off channel. charge injection charge injection is a measure of the glitch impulse transferred from the digital input to the analog output during switching. crosstalk crosstalk is a measure of unwanted signal that is co upled through from one channel to another as a result of parasitic capacitance. bandwidth bandwidth is the frequency at which the output is attenuated by 3 db. on response on response is the frequency response of the on switch. ac power supply rejection ra tio (acpsrr) acpsrr is a measure of the ability of a device to avoid coupling noise and spurious signals that ap pear on the supply voltage pin to the output of the switch. the dc voltage on the device is modulated by a sine wave of 0.62 v p - p. the ratio of the amplitude of signal on the output to the amplitude of the modulation is the acpsrr.
adg5208/adg5209 data sheet rev. a | page 20 of 24 trench isolation in the adg5208 / adg5209 , an insulating oxide layer (t rench) is placed between the nmos and the pmos transistors of each cmos switch. parasitic junctions, which occur between the transistors in junction isolated switches, are eliminated, and the result is a completely latch - up proof switch. in junction isolat ion, the n and p wells of the pmos and nmos transistors form a diode that is reverse - biased under normal operation. however, during overvoltag e conditions, this diode can become forward - biased. a silicon controlled rectifier (scr) type circuit is formed by the two transistors , causing a significant amplification of the current that , in turn, leads to latch - up. with trench isolation, this diode is removed, and the result is a latch - up proof switch. nmos pmos p well n well buried oxide layer handle wafer trench 09917-038 figure 37 . trench isolation
data sheet adg5208/adg5209 rev. a | page 21 of 24 a pplications informat ion the adg5 2 xx family of switches and multiplexers provide s a robust solution for instrumentation, i ndustrial, automotive, aerospace , and other harsh environments that are prone to latch - up, which is an undesirable high current state that can lead to device failure and persist until t he power supply is turned off. the adg5208 / adg5209 high voltage switches allow single - supply operation from 9 v to 40 v and dual - supply operation from 9 v to 22 v.
adg5208/adg5209 data sheet rev. a | page 22 of 24 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 38 . 16 - lead thin shrink small outline package [tssop] (ru - 16) dimensions shown in millimeters 2.70 2.60 sq 2.50 compliant t o jedec standards mo-220-wg gc. 1 0.65 bsc b o t t o m v i e w t o p v i e w 1 6 5 8 9 1 2 1 3 4 e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 0.45 0.40 0.35 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.20 min coplanari ty 0.08 pin 1 indica t or 0.35 0.30 0.25 for proper connection of the exposed pad, refer to the pin configura tion and function descriptions section of this data sheet. 08-16-2010-c figure 39 . 1 6- le ad lead f rame chip scale package [lfcsp_w q] (cp - 16 - 17 ) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adg5208 b ruz ?40c to +125c 16- lead thi n shrink small outline package [ tssop ] ru -16 adg52 08b ruz - rl7 ?40c to +125c 16- lead thin shrink small outline package [ tssop ] ru -16 adg5208bcpz - rl7 ?40c to +125c 16- lead lead frame chip scale package [lfcsp_ w q] cp -16-17 adg5209bcpz - rl7 ?40c to +125c 16- lead lead f rame chip scale package [lfcsp_w q] cp -16-17 adg5209 b ruz ?40c to +125c 16- lead thin shrink small outline package [ tssop ] ru -16 adg5209 b ruz - rl7 ?40c to +125c 16- lead thin shrink small outline package [ tssop ] ru -16 1 z = rohs compliant part.
data sheet adg5208/adg5209 rev. a | page 23 of 2 4 notes
adg5208/adg5209 data sheet rev. a | page 24 of 24 notes ? 2011 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09917 - 0 - 3/12(a)

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